The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor memory device. In more detail, the present invention relates to a method for forming an isolation structure in a flash memory device which is a non-volatile memory device.
The size of semiconductor devices has decreased as the semiconductor fabrication technology has improved. Accordingly, the size of active regions and field regions in a semiconductor device has also decreased. Thus, an aspect ratio of a trench formed in the field region has increased to secure an isolation characteristic in a semiconductor device in which an isolation structure is formed by performing a shallow trench isolation (STI) process. Consequently, it has become difficult to fill gaps in a uniformly formed isolation structure without generating a void using a single layer of a high density plasma (HDP) oxide layer, which is a typical isolation structure material, in a highly integrated semiconductor memory device smaller than 100 nm.
Thus, the trench is filled using a polysilazane (PSZ) layer, together with the solely used typical HDP oxide layer to improve a gap-fill characteristic of such isolation structure. The PSZ layer is a type of a spin on dielectric (SOD) layer formed by a spin coating method.
FIGS. 1A to 1F illustrate cross-sectional views of a typical method for forming an isolation structure in a semiconductor device using an HDP oxide layer and a PSZ layer. For instance, a typical method for forming an isolation structure in a flash memory device, which is a non-volatile memory device, is described. A cell region ‘CELL’ represents a region where a memory cell will be formed, and a peripheral region ‘PERIPHERAL’ represents a region where driving devices for driving the memory cell will be formed. At this time, a pattern density of the cell region is greater than that of the peripheral region.
Referring to FIG. 1A, a tunnel oxide-based pattern 11, a polysilicon pattern 12, and a pad nitride-based pattern 13 are formed over a substrate 10. In more detail, a tunnel oxide-based layer, a polysilicon layer for forming a floating gate, and a pad nitride-based layer are formed over the substrate 10 including the cell region and the peripheral region.
A hard mask 14 is formed over the pad nitride-based layer. The pad nitride-based layer, the polysilicon layer, the tunnel oxide-based layer, and the substrate 10 are etched using the hard mask 14 to form trenches (not shown) having a certain depth. Thus, the tunnel oxide-based pattern 11, the polysilicon pattern 12, and the pad nitride-based pattern 13 are formed. A first HDP oxide layer 15 is formed over the resultant structure to fill a portion of the trenches.
Referring to FIG. 1B, a PSZ layer 16 is formed to a large thickness over the first HDP oxide layer 15 such that the trenches are sufficiently filled.
Referring to FIG. 1C, a chemical mechanical polish (CMP) process, is performed to polish the PSZ layer 16 and the first HDP oxide layer 15 to expose upper surfaces of the pad nitride-based pattern 13. Reference numerals 16A and 15A refer to a polished PSZ layer 16A and a polished first HDP oxide layer 15A. The hard mask 14 (FIG. 1B) formed over the pad nitride-based pattern 13 is removed together with portions of the PSZ layer 16 and the first HDP oxide layer 15 during the CMP process.
Referring to FIG. 1D, a wet etch process is performed to etch the polished PSZ layer 16A to a certain depth. Reference numeral 16B refers to a remaining PSZ layer 16B. Portions of the polished first HDP oxide layer 15A may be etched while etching the polished PSZ layer 16A. Reference numeral 15B refers to a remaining first HDP oxide layer 15B. Thus, the remaining PSZ layer 16B having a certain thickness is formed over the remaining first HDP oxide layer 15B, and portions of inner sidewalls of the trenches are exposed. The polished PSZ layer 16A is etched to the certain depth because it is more difficult to polish PSZ than HDP oxide. Forming a HDP oxide layer having a sufficient polish characteristic than PSZ over the remaining PSZ layer 16B results in a sufficient polish characteristic during a subsequent CMP process. Thus, a height difference caused by the CMP process may be minimized.
Referring to FIG. 1E, a second HDP oxide layer 17 is formed to a large thickness over the resultant structure to sufficiently fill the trenches.
Referring to FIG. 1F, a CMP process is performed to polish the second HDP oxide layer 17 until the upper surfaces of the pad nitride-based pattern 13 are exposed. Reference numeral 17A refers to a remaining second HDP oxide layer 17A. Consequently, an isolation structure 18 including the remaining first and second HDP oxide layers 15B and 17A and the remaining PSZ layer 16B is formed. Although not illustrated, a wet etch process using a phosphoric acid (H3PO4) solution is performed to remove the pad nitride-based pattern 13.
However, the typical method for forming the isolation structure in the flash memory device shows a difficulty in process control when etching the PSZ layer using the wet etch process. Such difficulty is generated because the PSZ layer is a porous material and it is generally difficult to control a time period of the wet etch process to obtain an adequate height. Thus, an effective field oxide height (EFH) of a subsequent isolation structure may be irregular.